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Cache-Rings for Memory Efficient
Isosurface Construction

David M. Weinstein


Processor speeds continue to increase at faster rates than memory speeds. As this performance gap widens, it becomes increasingly important to develop ``memory-conscious'' algorithms - programs that still optimize instruction count and algorithmic complexity, but that also integrate optimizations for data locality and cache performance. In this paper we present a topological isosurface extraction algorithm which utilizes a ``cache-ring'' data structure to optimize memory performance. We compare our algorithm to an analogous edge-hashing algorithm which, though functionally equivalent, gives less priority to memory performance. While our algorithm actually executes more instructions during execution, we nonetheless see a speed-up over the traditional method, as we more-than-compensate for the extra instructions with superior memory performance.

Scientific Computing and Imaging
Wed Apr 23 17:39:06 MDT 1997